On Tue, Oct 25, 2011 at 5:14 PM, Herbert Graf wrote: > You have to look at the physical BRAM to see what's going on. > > Of hand: the BRAMs in the 3 series are I believe 9 or 18 bits wide. So, > if you only have an 8 bit bus, you won't use all the bits in one > particular BRAM (the ninth bit in each location will be wasted). > Silly me, I should have seen that coming. Thanks! > FWIW, I wouldn't use coregen to instantiate BRAMs. Just write verilog > that infers a memory and let the tool sort out BRAM usage. The added > benefit is your design won't be locked to one particular family, or > vendor, and if you parametrize things you will be able to change the > size of your memory in the future with just changing a few constants. > > Do you recommend just a plain register array? Or anything specific for that= ? --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .