On Tue, 2011-10-25 at 17:03 -0400, V G wrote:
> I'm trying to use the bram coregen from ISE. My part is the Spartan 3E 50=
0K
> gates with 20 of 18Kbit bram blocks for a total of 368640 bits (according=
 to
> the datasheet).
>=20
> However, the coregen isn't allowing me to fully use all available bits. B=
y
> trying different values, it shows me that (for example), an 8 * 2048 (=3D
> 16384 bits) memory consumes one 18Kbit block, which doesn't make sense to
> me. Going over just by one causes it to consume 2 blocks. What's going on
> here?
>=20
> It won't let me do an 8 * 46080 (=3D 368640) bits memory. It tells me tha=
t
> it's more than what's available on my device.

You have to look at the physical BRAM to see what's going on.

Of hand: the BRAMs in the 3 series are I believe 9 or 18 bits wide. So,
if you only have an 8 bit bus, you won't use all the bits in one
particular BRAM (the ninth bit in each location will be wasted).

FWIW, I wouldn't use coregen to instantiate BRAMs. Just write verilog
that infers a memory and let the tool sort out BRAM usage. The added
benefit is your design won't be locked to one particular family, or
vendor, and if you parametrize things you will be able to change the
size of your memory in the future with just changing a few constants.

TTYL

--=20
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