On Tue, 2011-10-25 at 13:07 -0400, V G wrote:

> Thank you for the reply. Is it necessary to specify direction for a
> module? If so, why must it be specified there, and not for as stated
> above in my code?=20

Direction is only specified in the port declaration list of a module.
For example, if you look at a really simply block like a flipflop:

module ff (input clk, input reset, input datain, output dataout);

reg dataout;

always @ (posedge clk)
begin
	if (reset)
		dataout <=3D 0;
	else
		dataout <=3D datain;
end
endmodule

You don't have to declare "wire" for nets, that's assumed by default. In
the above example, the synthesizer was treating dataout as a wire, until
it hit the "reg dataout" line, where it was redefined as a reg.

input, output, or inout only apply to nets leaving the module. So in
your case, clk_out is just a net in main, it isn't declared as input,
output or inout since it doesn't leave the module.

TTYL

--=20
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