On Tue, 2011-10-25 at 12:01 -0400, V G wrote:
> Hi Herbert,
>=20
>=20
> Quick question on what the default type of wire is in Verilog.
>=20
>=20
> This is my code that I quickly wrote to instantiate a DCM:
>=20
>=20
> `timescale 1ns / 1ps
>=20
>=20
> module main(
> input wire clk,
> output wire [7:0] Led
> );
>=20
>=20
> wire clk_out;
>=20
>=20
> reg [31:0] count;
>=20
>=20
> assign Led[7:0] =3D count[27:20];
>=20
>=20
> clk_1 my_clk_1(
> .CLKIN_IN(clk),
> .CLKFX_OUT(clk_out)
> );
>=20
>=20
> always @(posedge clk_out)
> begin
> count =3D count + 1;
> end
>=20
>=20
> endmodule
>=20
>=20
>=20
>=20
>=20
>=20
> It works. Where I wrote "wire clk_out", what is the type of wire? Is
> it output, input, or inout, or what?


Please note what I'm about to say is skipping over some details, but
from a synthesizer code perspective is pretty much spot on:

There are 2 types of nets in verilog, the default is "wire" (i.e. all
inputs and outputs of a module are of type wire unless defined later as
type reg), the other is "reg".

The only real difference from your perspective between the 2 is "wire"s
can only be driven by instantiated blocks or assign statements. "reg"s
can only be driven by always blocks.

A net in verilog is bidirectional, there is no defined direction.

input, output and inout are only applicable to a module.

TTYL

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.