At 10.06 2011.10.24, you wrote:
>
>On Oct 24, 2011, at 12:55 AM, Electron wrote:
>
>> As you can see coding in assembly is actually easier on the PIC32 =20
>> than on
>> the PIC24 or dsPIC30/33 or even more on the PIC.
>
>
>Thanks for the pointer.
>
>> I don't like the asm syntax and it
>> doesn't even look that good vs ARM or other RISC architectures, but =20
>> then
>> benchmarks seem to be all in favour of MIPS.
>
>I've been reading up on ARM and MIPS architectures recently, and I =20
>noticed the same thing.  MIPS doesn't LOOK like it would turn out to =20
>be more efficient than ARM.  Is there analysis somewhere explaining =20
>why it is anyway?  Maybe it's those "immediate operand" instructions.

My idea, but please take it with a grain of salt, is that ARM is superior
but hardly exploitable by complier technology.

Then, by taking a deeper look at MIPS (which I studied 20 years ago and
almost forgot all of it) we can notice that it has some clever instructions
too, so it's not as "simple mind" as it easily appears at the begin.

Please consider also that the PIC32 scores very well vs other ARM MPU's
not only because of MIPS vs ARM, but (IMHO) mostly because Microchip really
did a good job with it, by using multiple buses, high performance mul/div
and other technical solutions that really unleash all the potential of the
M4K core. It looks like in this regard the ARM MPU's manufacturer have much
less care than Microchip did. Also, the Microchip peripherals are good
compared to other MPU's (although I really wish they made them 32bit like
the core, but I won't bother), so all in all, price considered, power
consumption considered, and CPU power, peripherals and configurability
considered, the PIC32 now seems to me a really really nice high perf MPU.

They are going to release SDIP low pin count (>=3D28 pin IIRC) PIC32's soon=
,
so it'll become even more interesting.


>I had to do a web search for how to do multi-precision arithmetic on =20
>MIPS.
>There's no carry flag, so it's sorta gross.  I'm still not sure I =20
>actually believe it works all the time :-(  I never thought the PIC16 =20
>weirdness where there was a carry flag but no "add with carry" =20
>instruction would look good...

Multi-precision arithmetic for me is very important, even of a 32bit CPU.
One thing that disappointed me is that although the PIC32 MIPS core has
32bit*32bit=3D64bit MULs, it only has 32bit/32bit=3D32bit DIVs, not 64/32.
However, there's always a limit on the word size of any CPU, so
multi-precision arithmetic is something that must always be taken
into account.

Yes, as incredible as it may seem, the MIPS lacks a carry flag. This is
a distinctive advantage for  out-of-order-register-renamed designs,
although I'm not sure if they made this design choice at that time because
of this. ;-)

Personally I think it would be much wiser (from a "best bang for the buck"
design logic) to implement multiple cores than to pretend from a single cor=
e
to execute more than one instruction per cycle. However, my model doesn't
fit with old software, of course.

Regarding MIPS multiprecision arithmetic, you can do it e.g. this way:

	addu	alow, blow, clow
	sltu	tmp, alow, clow		(set tmp =3D 1 if alow < clow, else 0)
	addu	ahigh, bhigh, chigh	*
	addu	ahigh, ahigh, tmp

If you ask me, I'd prefer to have the carry bit any time, but unfortunately
we don't have it on the MIPS. I just wanna make it clear that multiprecisio=
n
arithmetic is entirely possibly on the MIPS of course, although not as
efficiently as an hypotethic:

	addu	alow, blow, clow
	addcu	ahigh, bhigh, chigh


>BTW, I thought the new 16bit PICs had lower power consumption.  A =20
>random PIC24H datasheet says <50mA when running 40mips...

Thanks for the hint, I really need to take a look at this option too then,
as I don't really need the DSP core for this project, and a 24F would be OK
too.

Thanks again!

Cheers,
Mario

>
>BillW
>
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