> -----Original Message-----
> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On
Behalf
> Of John Sanderson
> Sent: 20 October 2011 13:27
> To: Microcontroller discussion list - Public.
> Subject: Re: [PIC]: SPI problem on dsPIC33FJ64GS610
>=20
> Hello Sean & PIC.ers,
>=20
> I am chiming in late to this thread..  but this might be relevant.
>=20
> I have a long series of products in the field using the 18Fxxx and
> AD7715 adc. The SPI i/f is driven in s/w by the 18F and the data
> comes out the adc on SDO to a pic pin (can't remember which but
> it is not in portb).
> I had *assumed* that the adc SDO line would act like an output always
> should, low impedance etc. all the time as it is a hardware function
> of the adc.
> It was a big surprise to find that node floating at the end of
> transfers, the pic i/o pin was trised for input so it was always
> hi-Z as well.

It should come as no surprise to see the data output pin of an SPI slave
device in a high impedance state after de-asserting the chip select (or
possibly after the last bit transferred in a frame on some devices).  If
this were not the case, you would be unable to connect multiple slaves
to the same SPI bus, since there would be a conflict between slaves
trying to assert different levels.

Regards

Mike

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