At 09.52 2011.10.17, you wrote:
>ARM is not particularly beautiful imho. Orthogonality is a hallmark of all
>well-designed RISC cpus. I don't know if PDP11 falls under this category a=
s it
>has pre and post-increment and also conditional branching on nearly all cp=
u
>registers.

Talking about orthogonality, the 680x0 is very orthogonal too, and the VAX =
as
well. Both are CISC designs. The VAX is the evolution of the PDP11, which w=
as
already quite orthogonal, with the exception of floating point instructions
(notably, the VAX made them orthogonal too).

Accumulator-based designs aren't (this is true virtually always) orthogonal=
,
and since many CISC are accumulator based, this gave CISC's the reputation =
of
not being orthogonal.

I think that orthogonality has really nothing to do with CISC or RISC. Also=
,
although I think it's a quality, I don't think it should be a goal when des=
igning
a CPU.

What I like of ARM is that in the hands of a skilled asm programmer allows =
you
to do more tricky and cool things than with other RISC CPU's. It's funny bu=
t it
is not necessarily compiler friendly, so to speak. ;)

Wikipedia reports some emblematic examples:

The standard example of this is the subtraction-based Euclidean algorithm: =
ARM address mode

In the C programming language, the loop is:

    while(i !=3D j) {
       if (i > j)
           i -=3D j;
       else
           j -=3D i;
    }

In ARM assembly, the loop is:

 loop   CMP    Ri, Rj       ; set condition "NE" if (i !=3D j),
                            ;               "GT" if (i > j),
                            ;            or "LT" if (i < j)
        SUBGT  Ri, Ri, Rj   ; if "GT" (greater than), i =3D i-j;
        SUBLT  Rj, Rj, Ri   ; if "LT" (less than), j =3D j-i;
        BNE    loop         ; if "NE" (not equal), then loop

which avoids the branches around the then and else clauses. Note that if Ri=
 and Rj are equal then neither of the SUB instructions will be executed, op=
timising out the need for a conditional branch to implement the while check=
 at the top of the loop, for example had SUBLE (less than or equal) been us=
ed.

One of the ways that Thumb code provides a more dense encoding is to remove=
 that four bit selector from non-branch instructions.

---

Another feature of the instruction set is the ability to fold shifts and ro=
tates into the "data processing" (arithmetic, logical, and register-registe=
r move) instructions, so that, for example, the C statement

a +=3D (j << 2);

could be rendered as a single-word, single-cycle instruction on the ARM.

ADD     Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with few=
er memory accesses; thus the pipeline is used more efficiently. Even though=
 the ARM runs at what many would consider to be low speeds, it nevertheless=
 competes quite well with much more complex CPU designs.

The ARM processor also has some features rarely seen in other RISC architec=
tures, such as PC-relative addressing (indeed, on the ARM the PC is one of =
its 16 registers) and pre- and post-increment addressing modes.

Another item of note is that the ARM has been around for a while, with the =
instruction set increasing somewhat over time. Some early ARM processors (b=
efore ARM7TDMI), for example, have no instruction to store a two-byte quant=
ity, thus, strictly speaking, for them it's not possible to generate effici=
ent code that would behave the way one would expect for C objects of type "=
int16_t".

---

Weirdly, I had worked on it at the times of the Archimedes, but not in the =
embedded market. I am now restarting to code (in asm) on the ARM because I =
wanna code Android apps (also) in asm, and rediscovering the (IMHO) beautie=
s of it.

Cheers,
Mario

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