Em 17/10/2011 16:11, Electron escreveu:
> Hi all,
> I have a dsPIC30F based design where power consumption is critical. But t=
he
> very high clock that I need is justified only by a part of the design, i.=
e.
> that I need a 32bit timer with the best time-resolution possible. Basicly
> I'm recording when some events take place (timestamp), a bit like a logic
> analyzer but the events are considerably less frequent (around 1000Hz max=
),
> however as I said I need very good resolution (around 35-40ns is my goal)=
..
>
> This could be achieved by the dsPIC, pairing Timer2 and Timer3 into a 32b=
it
> timer (or using interrupts to simulate the higher word timer), but the po=
wer
> consumption at 25-30MHz is very high, way too high, and SLEEP mode disabl=
es
> clocks anyway, so forget about using it, and IDLE mode still consumes a l=
ot.
>
> I thought about using an external oscillator both as a system clock and a=
s
> Timer1 asynchronous input.
>
> Has anyone ever tried to use the Timer1 as a high resolution time stamp
> counter, with the DSC most of the time sleeping? Any quirks? Or hints?
>
> This said, I've looked at the data sheets of all the 5V oscillators I cou=
ld
> find, but they consume tens of mA's. Probably they mean only at max outpu=
t
> load, but this is not specified in the data sheet. How much current does =
a
> typical 5V osc really draw? Can you suggest me a 5V osc (best 7.3728MHz) =
that
> draws as little current as possible?
>
> This way I could get timer1 counting cycles (till PR1=3D0x8000 interrupt,
> which will wake up the DSC and allow me also to increment with the CPU th=
e
> higher bits of the time stamp counter), SLEEP as much as I need, and be
> waken up by the timer every 0x8000 cycles or by a CNx event.
>
> Do you think it is achievable?
>
> No I can't use an FPGA, I'd like it, it would be trivial, but it's overki=
ll,


An FPGA isn't necessary. A small CPLD would be enough.


> I must use what I have (the dsPIC), the most I can do is to opt for an
> external oscillator in place of the typical XTAL. No more chips.. althoug=
h
> I wish a high resolution serial time stamp counter IC existed, it would b=
e
> very useful for some projects. It would detect edges from its inputs and
> record in a FIFO when they took place, then you would load serially this
> info back into the DSC/MPU. I doubt such a chip exists (at least at high
> resolutions, i.e. tens of ns range), but anyway even if I can't use it fo=
r
> this project, if such a chip exists I'd like you to tell me! :-)
>
> What about my Timer1 + ext oscillator design.. do you think it's a winner=
?
> I wish I can stay below 10 mA total power consumption.. as I said the 30F
> will sleep most of the time, but events must be timed very accurately.


Why not using a 33F? They are faster and consume less power.


Isaac

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