On Sun, Oct 9, 2011 at 11:12 PM, Martin Darwin <martin@davintech.ca> wrote:

> SDRAM Have to refresh. Probably not great for a logic analyzer unless the
> ram is a lot faster than your sample time. Not hard to interface to & lot=
s
> of specs/ models  out there.
>
>
Xilinx's memory interface generator should generate all the code necessary
to interface it and refresh it.
--=20
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