On Mon, Oct 3, 2011 at 7:19 PM, peter green <plugwash@p10link.net> wrote:

> V G wrote:
> > I know that FPGAs aren't *meant* to do this, and this is the sort of
> thing
> > that microcontrollers do, but what's the best way to get an FPGA to
> execute
> > some sequence of codes (in Verilog).
> >
> > For example:
> >
> > write 0x00 to port A
> > sleep 10ms
> > write 0x0F to port A
> > sleep 10ms
> > read port A to memory (either block RAM or SRAM)
> >
> >
> > I've read about state machines, but what else?
> >
> State machines are how you do it.
>
> Typically you would have a state register (basically an integer that you
> only ever set to constants) which indicates the current state. Each
> state represents a step in your sequential process.
>
> You then have a block that runs on the clock and has a case statement
> based on the state variable. Each case performs a step of your program.
>
> something like (syntax may be slightly off, it's a while since i've
> written verilog)
>
> always @ (posedge reset or posedge clock)
> if (reset) begin
>  // reset state
>  state <=3D 00;
> end else begin
>  // set default outputs
>  write_strobe_porta <=3D 0;
>  write_strobe_mem <=3D 0;
>  case state
>    00: begin
>      write_data_porta <=3D 0x00;
>      write_strobe_porta <=3D 1;
>      counter <=3D 0;
>      returnstate <=3D 10
>      state <=3D 100; // 10ms countdown timer
>    end
>    10: begin
>      write_data_porta <=3D 0x0F;
>      write_strobe_porta <=3D 1;
>      counter <=3D 0;
>      returnstate <=3D 20;
>      state <=3D 100
>    end
>    20: begin
>      write_data_mem <=3D read_data_porta;
>      write_address_mem <=3D 0xDEAD;
>      write_strobe_mem <=3D 1;
>      state <=3D 30;
>    end
>    30: begin
>      //wait forever in this state, in a real system you might want to
> include something to restart
>      //the process other than using the asynchronous reset signal
>    end
>
>
>    100: begin
>      if (counter < (10*COUNT_MS)) begin
>        counter++;
>      end else begin
>        state <=3D returnstate;
>      end
>    end
>  endcase
> end
>
>
> Notes:
>
> 1: you should not try to do any arithmetic or other clever stuff with
> the state variable as doing so will (at least in the case of quartus)
> stop the synthisiser recognising it as a state variable and doing state
> machine optimisation. The only things you should do to the state
> variables is set them to constants, set them to each other and write
> conditionals based on them. If you need a counter (you almost certainly
> will) then it should be seperate from the state variable.
> 2: Don't worry about the actual encoding of states to bit patterns. that
> is the synthisizers job. It's prudent to leave gaps in your state
> numbering so you can insert new states if needed (think like how in old
> fassioned basic programs you used to number lines in increments of 10).
> 3: In general in sequential code you should use nonblocking assignments
> (assignments which take effect at the end of the current time step).
> 4: time delays are measured by counting clock cycles. While verilog has
> a way of specifying absoloute time delays this is not supported by
> synthisizers (or the hardware they synthisize for) so it should only be
> used in code that does not have to be synthisised (such as testbench code=
).
> 5: remember fundamentally you are designing hardware. If two state
> machines need to access the same thing it is YOUR problem to route the
> signals corectly and to make sure they don't step on each other
> Signalling between different state machines and other blocks of logic is
> typically done with strobe signals.
>
> > And yes, microblaze is the obvious answer, but I mean *other* than that=
..
> >
>
>
Thank you VERY much. This is exactly what I'm looking for. Would have taken
hours or days to google.
--=20
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