V G wrote:
> I know that FPGAs aren't *meant* to do this, and this is the sort of thin=
g
> that microcontrollers do, but what's the best way to get an FPGA to execu=
te
> some sequence of codes (in Verilog).
>
> For example:
>
> write 0x00 to port A
> sleep 10ms
> write 0x0F to port A
> sleep 10ms
> read port A to memory (either block RAM or SRAM)
>
>
> I've read about state machines, but what else?
>  =20
State machines are how you do it.

Typically you would have a state register (basically an integer that you=20
only ever set to constants) which indicates the current state. Each=20
state represents a step in your sequential process.

You then have a block that runs on the clock and has a case statement=20
based on the state variable. Each case performs a step of your program.

something like (syntax may be slightly off, it's a while since i've=20
written verilog)

always @ (posedge reset or posedge clock)=20
if (reset) begin
  // reset state
  state <=3D 00;
end else begin
  // set default outputs
  write_strobe_porta <=3D 0;
  write_strobe_mem <=3D 0;
  case state
    00: begin
      write_data_porta <=3D 0x00;
      write_strobe_porta <=3D 1;
      counter <=3D 0;
      returnstate <=3D 10
      state <=3D 100; // 10ms countdown timer
    end
    10: begin
      write_data_porta <=3D 0x0F;
      write_strobe_porta <=3D 1;
      counter <=3D 0;
      returnstate <=3D 20;
      state <=3D 100
    end
    20: begin
      write_data_mem <=3D read_data_porta;
      write_address_mem <=3D 0xDEAD;
      write_strobe_mem <=3D 1;
      state <=3D 30;
    end
    30: begin
      //wait forever in this state, in a real system you might want to incl=
ude something to restart=20
      //the process other than using the asynchronous reset signal
    end

   =20
    100: begin
      if (counter < (10*COUNT_MS)) begin
        counter++;
      end else begin
        state <=3D returnstate;
      end
    end
  endcase
end


Notes:

1: you should not try to do any arithmetic or other clever stuff with=20
the state variable as doing so will (at least in the case of quartus)=20
stop the synthisiser recognising it as a state variable and doing state=20
machine optimisation. The only things you should do to the state=20
variables is set them to constants, set them to each other and write=20
conditionals based on them. If you need a counter (you almost certainly=20
will) then it should be seperate from the state variable.
2: Don't worry about the actual encoding of states to bit patterns. that=20
is the synthisizers job. It's prudent to leave gaps in your state=20
numbering so you can insert new states if needed (think like how in old=20
fassioned basic programs you used to number lines in increments of 10).
3: In general in sequential code you should use nonblocking assignments=20
(assignments which take effect at the end of the current time step).
4: time delays are measured by counting clock cycles. While verilog has=20
a way of specifying absoloute time delays this is not supported by=20
synthisizers (or the hardware they synthisize for) so it should only be=20
used in code that does not have to be synthisised (such as testbench code).
5: remember fundamentally you are designing hardware. If two state=20
machines need to access the same thing it is YOUR problem to route the=20
signals corectly and to make sure they don't step on each other=20
Signalling between different state machines and other blocks of logic is=20
typically done with strobe signals.

> And yes, microblaze is the obvious answer, but I mean *other* than that.
>  =20

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.