One other thing.  The RAMS I am talking about are 128K 9 bit locations.
 Which means there are 1179648 bits.
 Not 128K bits.  In other words, I cascaded two of the 128K RAMS for a
total of 256K.  Each channel of the
 analyzer is connected to a data line on the RAMS.  I had 4 of these two
RAM setups in parallel.  This gives
 me 36 channels, each with 256K samples.   I used this many times before
I was able to afford a commercially
 built unit.  And if I still had it (I gave it to a student friend of
mine a few years ago), I would still
 use it.  In some respects, it was better than the commercial unit.

 The bottom line is in the projects I worked on, 256K samples was more
than enough.  I could specify what I
 wanted to trigger on by setting a pattern on any or all of the input
channels, and the unit would trigger
 when that pattern would appear.  Until that pattern appeared on the
input lines, the data would come in and
 the RAMS would record the level, but only after the pattern appeared
would the unit mark the beginning of
 the record, and would stop when the RAMS were full.

 In other words, until the trigger event happened, data would come in
and if the max address range of the=20
 RAMS were exceeded, the counter would wraparound and over write the
existing data.  After the trigger event
 appeared, the current address of the RAM was flagged, and you would
continue collecting data up to the end
 of the RAM.  If you wanted to see the pre trigger data, that could be
reviewed up to a point.  But you had\
 to select the pretrigger  option if you wanted to see pretrigger data.=20
Otherwise, you would see only post
 trigger data.

 I built this unit based on a magazine article, but I added some
enhancements of my own.  I may still have
 the article if you'd be interested.  I'd have to look for it though.


 Regards,

 Jim

> -------- Original Message --------
> Subject: Re: [PIC] PIC32 USB - for logic analyzer
> From: V G <x.solarwind.x@gmail.com>
> Date: Thu, September 29, 2011 12:17 pm
> To: "Microcontroller discussion list - Public." <piclist@mit.edu>
>=20
>=20
> On Thu, Sep 29, 2011 at 12:48 PM, Mark Rages <markrages@gmail.com> wrote:
>=20
> > On Thu, Sep 29, 2011 at 10:29 AM,  <jim@jpes.com> wrote:
> > >
> > >  I built a logic analyzer many years ago that used an oscillator that
> > > would increment the address counter
> > >  of some dual port cache RAMS.  You could capture using one port of t=
he
> > > ram chip, and output the data on the
> > >  other port.  The dual port rams were from Cypress IIRC, and I believ=
e
> > > they were 128K x 9.  I used the 9th
> > >  bit as a trigger capture bit. After the capture, I would then send t=
he
> > > captured data out to the PC for
> > >  display. It worked well.   You might try looking at some of these RA=
M
> > > chips.  Again, IIRC, they would work
> > >  up to about 60 Mhz or so.
> > >
> >
> > Microchip has some serial RAMs that do this.  Just keep clocking them
> > and they store a bit with each clock.  Design here:
> > http://dangerousprototypes.com/docs/Logic_Shrimp_design_overview
> >
> >
> The only problem I have with these is that 256K samples isn't enough. I c=
an
> store 250k samples on the PIC32 RAM itself if I wanted to. I either need =
to
> stream it to the host on the fly, or need some cheap DRAMs.
> --=20
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