At 09:07 AM 9/20/2011, V G wrote: >You're not the first. I found it a long-ass time ago. I can't stand that >site. You know, VG, that you are starting to look like=20 a really bad imitation of Olin Lathrop, except without his smarts. You are definitely entitled to your own=20 opinion. However, I really don't like it when=20 you slam somebody for no particular reason. For what its worth, I purchased two of those=20 little, really inexpensive 32 channel logic=20 analyzers. They provide astonishing performance for mere peanuts. I've mentioned them on the PIClist previously,=20 but here is a repeat of that information: I don't know if you have come across something=20 called the Open-bench Logic Sniffer (OLS) but its=20 an open-source logic analyzer based on a PIC and=20 a FPGA. Its good for up to 32 channels but the=20 board itself contains only enough 5V-tolerant=20 buffer inputs for 16 channels. The other 16=20 channels are brought out to headers: you can use=20 them directly for 3.3V signals or add on an=20 inexpensive daughter board containing another channels of 5V-tolerant buffe= r. Here's the kicker: it costs $50 including=20 shipping to anywhere in North America (and most=20 of the rest of the world). Probe sets cost an=20 extra $6 per input cable of 8 clips +=20 ground. The daughter-board adding 16 more=20 buffered input channels is an extra $15. Although the firmware is currently evolving, the=20 current stable firmware is eminently=20 usable. There are two distinct software=20 platforms available for it: SUMP and something=20 expressly designed for the OLS by a forum member with username of jawi. The first shipping version has FPGA code written=20 by somebody who is not particularly=20 experienced. It works but the performance is=20 less than what is actually possible. The current beta firmware was written by somebody=20 who actually designs large FPGA systems for a=20 living. He has apparently gotten almost all of=20 the features of an Agilent HP 16550a analyzer into the unit. Short-list of specs: single-data-rate (max) 100=20 MHz, double-data-rate sample rate (max) 200 MHz, Here's the new firmware author's take on what he has done: "My version of the fpga uses 85% of the slices,=20 keeps the legacy triggers, meets timing easily (at 105Mhz), and adds: Trigger Terms: 10 more 32-bit masked value comparisons. 2 range checks. 2 edge checks (rising, falling, both, neither). 2 36-bit timers (10ns to 600sec range). States: 16 state FSM Each state can use any combination=20 (AND/NAND/OR/NOR/XOR/NXOR) of the trigger terms=20 for detecting a =93hit=94 condition, and =93else=94 condition, or =93captur= e=94 condition. Each state also has a 20-bit hit count that must=20 be reached before a full =93hit=94 occurs. Hit=20 actions include setting trigger(run), starting/stopping timers, and advancing to the next state. The =93else=94 condition lets you punt to another state. The =93capture=94 condition lets you control what=20 gets sampled into RAM, until you flip the trigger. =85Grab the 16550a user=92s guide. I think you'll be=20 surprised how much got squeezed in." Overview: In-depth description:=20 Even more hardware detail=20 Stable firmware:=20 Beta firmware: Windows software:=20 ordering:=20 There is also a download available for the SUMP=20 software - I can find that for you if you want. Bottom line: you get a REALLY full-featured logic analyzer for peanuts. I've been using mine since last fall and I'm=20 thrilled with it. I can finally retire my ancient Tek unit. dwayne PS - these are the same guys who designed the Bus=20 Pirate that a lot of us have been using to do a=20 myriad of prototyping projects with. dwayne --=20 Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax www.trinity-electronics.com Custom Electronics Design and Manufacturing --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .