Hi all,

I want to make a logic analyzer from either or both of my PIC32 board
(UBW32) and Xilinx Spartan 3E XC3S500E board (Nexys 2). I initially wanted
to make it to analyze the signals from my electric shaver charging station
as well as laser printer cartridge chips.

Anyway, I don't think a general purpose use logic analyzer needs to be that
fast (not for my purposes anyway).

1. The PIC32 can run up to 80MHz as far as I know. The logic analyzer will
consist of sampling as fast as it can and either streaming it to external
RAM or directly over full-speed USB to the PC. The PIC should be able to
stream at least 5Mbit/s over full-speed USB. I can safely say at least 5Msp=
s
using this thing. Should be pretty easy for me to do.

2. The Spartan 3 can run up to 333MHz. I'm not too good with FPGAs yet, so
this will be a challenge for me. I know one can design to sample on the
rising edge AND falling edge of the clock. *Does this mean 666Msps is
possible?* Just curious. I'll probably design it to run at 10 or 20Msps
anyway. It'll then directly stream to the onboard 16M DRAM which can operat=
e
at 80MHz in synchronous mode or 70ns time in asynchronous mode. Not too sur=
e
about the differences yet, but I know it's more than capable of streaming i=
n
the data. *What is the difference between asynchronous and synchronous
modes?* I googled, and didn't come up with much. I know that in synchronous
mode, the RAM is synchronized to the clock and changes occur on clock edges=
..
In asynchronous mode, it is "level sensitive", whatever that means, and
isn't synchronized to the clock. I've read that synchronous mode is faster,
but why? What's the concept behind it? 16MB is plenty to buffer lots of
sampling time. I could potentially code in a real time compressor to
compress logic streams where multiple samples show the same value. Should
save a lot of space and allow for much more storage. This thing also has a
high speed USB2 interface, so I could also stream the data to the computer
at high speed if I want.

Looks like I'll go with the FPGA option.

Just getting my thoughts out.

Any comments appreciated.
--=20
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