a) Ensure the ground connection connects before any other signals,
perhaps making it longer or using a special connector;
b) Put a series resistor (between 33R and 100R for fast signals, more
for slow signals) in each logic signal that crosses from one board to
another;
c) If possible, put a diode in series with the power signals;
d) Put a TVS from each signal to ground.


Best regards,

Isaac



Em 13/9/2011 21:16, Brent Brown escreveu:
> Having a little problem, thought I would share for interest and maybe som=
eone has=20
> been here before.
>
> Two boards, both of my deisgn. The base board has Silicon Labs C8051F120=
=20
> processor running on 3.3V (not a PIC, hence EE tag). Recent revision adde=
d an 8=20
> way header to allow a daughter board (factory option) to be plugged in to=
 add extra=20
> featrues. Header provides +12V (motors etc), +5V, +3.3V and GND connectio=
ns to=20
> supply power, and RXD and TXD for comms (3.3V level).
>
> Newly designed daughter board sits on top of previously described board a=
nd=20
> connects by way of 0.1" header pins. Also has Silicon Labs processor (C80=
51F121)=20
> runs off 3.3V supply, communicates over RXD and TXD to main processor (al=
so=20
> running at 3.3V), no need for any regulators etc on daughter board.
>
> Problem: Hot plugging daughter board onto the main board fries the microc=
ontroller=20
> on the main board. Happened twice now. First time it was me: forgot that =
12V=20
> supply to main board is battery backed, so installed daughter board while=
 I thought=20
> power was off. Ok, make a note: don't do this again.
>
> Second time customer shipped the product, end user noted shipping had cas=
ued=20
> the daughter board to come loose, re-seated it without removing 12V batte=
ry first.=20
> Same result, dead main processor (won't respond to JTAG programmer, repla=
ce=20
> chip all is fine).
>
> What I strongly suspect is happening is that plugging into header pins th=
e GND pins=20
> are not contacting first (there is nothing to guarantee the order of conn=
ections) and=20
> when +12V pin contacts is couples power through discharged elelctrloytic =
caps on=20
> daughter board to GND rail, then "backfeeds" to +3.3V rail through intern=
al body=20
> diodes of chips on that rail, pushing up the +3.3V rail and popping the p=
rocessor on=20
> the main board. Similar could be happening on RXD, TXD and +5V rail... bu=
t nature=20
> of 2 failures so far suggest +3.3V rail more likely.
>
> Solutions:
> 1. Don't hot plug the board
> 2. Fix the daughter board in place more solidly
> 3. Raise the height of the GND pins so they are more likely to contact fi=
rst
>
> Other:
> - Have opportunity now to modify daughter board design now before going t=
o full=20
> production, but seems would have to add an unreasonable amount of circuit=
ry to=20
> isolate during power up +3.3V, +5V, RXD and TXD.
> - Prefer not to re-design main board, even so I suspect it would not be t=
rivial to add=20
> comprehensive protection.
>
> For I'm going with 1 and 2 above, looking at the feasibility of 3. Keen t=
o hear any=20
> other ideas~!
>

--=20
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