Having a little problem, thought I would share for interest and maybe someo=
ne has=20
been here before.

Two boards, both of my deisgn. The base board has Silicon Labs C8051F120=20
processor running on 3.3V (not a PIC, hence EE tag). Recent revision added =
an 8=20
way header to allow a daughter board (factory option) to be plugged in to a=
dd extra=20
featrues. Header provides +12V (motors etc), +5V, +3.3V and GND connections=
 to=20
supply power, and RXD and TXD for comms (3.3V level).

Newly designed daughter board sits on top of previously described board and=
=20
connects by way of 0.1" header pins. Also has Silicon Labs processor (C8051=
F121)=20
runs off 3.3V supply, communicates over RXD and TXD to main processor (also=
=20
running at 3.3V), no need for any regulators etc on daughter board.

Problem: Hot plugging daughter board onto the main board fries the microcon=
troller=20
on the main board. Happened twice now. First time it was me: forgot that 12=
V=20
supply to main board is battery backed, so installed daughter board while I=
 thought=20
power was off. Ok, make a note: don't do this again.

Second time customer shipped the product, end user noted shipping had casue=
d=20
the daughter board to come loose, re-seated it without removing 12V battery=
 first.=20
Same result, dead main processor (won't respond to JTAG programmer, replace=
=20
chip all is fine).

What I strongly suspect is happening is that plugging into header pins the =
GND pins=20
are not contacting first (there is nothing to guarantee the order of connec=
tions) and=20
when +12V pin contacts is couples power through discharged elelctrloytic ca=
ps on=20
daughter board to GND rail, then "backfeeds" to +3.3V rail through internal=
 body=20
diodes of chips on that rail, pushing up the +3.3V rail and popping the pro=
cessor on=20
the main board. Similar could be happening on RXD, TXD and +5V rail... but =
nature=20
of 2 failures so far suggest +3.3V rail more likely.

Solutions:
1. Don't hot plug the board
2. Fix the daughter board in place more solidly
3. Raise the height of the GND pins so they are more likely to contact firs=
t

Other:
- Have opportunity now to modify daughter board design now before going to =
full=20
production, but seems would have to add an unreasonable amount of circuitry=
 to=20
isolate during power up +3.3V, +5V, RXD and TXD.
- Prefer not to re-design main board, even so I suspect it would not be tri=
vial to add=20
comprehensive protection.

For I'm going with 1 and 2 above, looking at the feasibility of 3. Keen to =
hear any=20
other ideas~!

--=20
Brent Brown, Electronic Design Solutions
16 English Street, St Andrews,
Hamilton 3200, New Zealand
Ph: +64 7 849 0069
Fax: +64 7 849 0071
Cell: +64 27 433 4069
eMail:  brent.brown@clear.net.nz


--=20
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