Are you sure of that?  I've not seen it documented anywhere, but I have=20
set interrupt flags to generate an interrupt.

For example, using interrupt on PortB change to read an encoder. =20
Reading/writing PortB for other I/O can cause the interrupt to fail to=20
occur.  By keeping track of the state phase A and B were in at the last=20
interrupt, you can detect if a change happened that failed to cause an=20
interrupt.  You can then set RBIF =3D 1 and cause an interrupt.  I know=20
for sure it works that way for 16F chips, and see no reason it wouldn't=20
work with 18F as well.

Kerry



John Temples wrote:
> On Thu, 1 Sep 2011, Nathan House wrote:
>
>  =20
>> 		PIR1bits.RCIF =3D 0; // clear the USART receive interrupt flag
>>    =20
>
> RCIF is a read-only bit.  You cannot write a zero to it.  It reflects
> the state of RCREG: set when there is data waiting to be read, clear
> when there isn't.
>
> TXIF is also read-only.
>
> --
> John W. Temples, III
>  =20

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.