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Another couple of things to slow me down with the dsPIC33...802

Below is the set-up for the SPI module, following that a little code

Attached is the analyser capture of two versions of that code. The top
group, waiting for SPIRBF to set, the lower group not waiting

The two things -

(1) the device is sending the correct response, 0x01, at the correct time
(the second byte of SCKs) but it doesn't appear that the data gets into
SPIBUF through the pin. TRISB is set only once, and it would appear
to be an input as the signal on SDI is good. Setting RP11 as SDI, well,
I have to assume that the connection is made inside the PIC. The Unlock
sequence has been done. The UART is remapped and that works fine,
as do SCK and SDO come out of the assigned pins

(2) why does SPIRBF appear to be set after the first set of 8 SCK and
yet not after the second ? It might possibly be that (1) is true - new data
is not getting into the shift register after the first read of SPIBUF and s=
o
therefore the flag will not be re-set

Tried 3 PICs, all new, no change, so it'll be something I'm doing or not
doing, but I've not spotted it yet. And I can't see anything else that need=
s
to be done to remap, and particularly as all the other pin assignments
work anyway. I don't want to assume that because there's a recognised
fault with SPITBF that there could be a silicon gotcha with SDI

Any thoughts ?

Someone with a similar problem, but with SDI on RB0

http://www.microchip.com/forums/m594951.aspx

Joe

           mov     #0b0000100000001010,w0
;                     0000
;                         1                 SDI1
;                          0                /CS
;                           0
;                            0              SCK1
;                             0             SDO1
;                               0           En
;                                0          RS
;                                 1         /CTS (in)
;                                  0        TX
;                                   1       RX
;                                    0      /RTS (out)
           mov     w0,TRISB

; SPI Din   b7  SDO1 00111 RPn tied to SPI1 Data Output
;     Clk   b8  SCK1 01000 RPn tied to SPI1 Clock Output
;     /CS  b10  SPI /SS
;     Dout b11  SPI1 RPINR20 SDI1R<4:0>, data from card
;
; RP7  =3D Din (card), SDO o/p
; RP8  =3D Clk         SCK o/p
; RP10 =3D /CS         /SS o/p
; RP11 =3D Dout (card) SDI i/p

           mov     #0b0000011100000000,w0
;                     ---00111---xxxxx     ;RP7 as SDO1
           mov     w0,RPOR3

           mov     #0b0000000000001000,w0  ;RP8 as SCK1
;                     ---xxxxx---01000
           mov     w0,RPOR4

           mov     #0b0000000000001011,w0
;                     ---xxxxx---01011     ;RP11 as SDI1
           mov     w0,RPINR20


           mov     #0b1000000000000000,w0
;                     1                     SPI enable
;                      x
;                       0                   discontinue in idle
;                        xxxxxx
;                              x            SPIROV flag
;                               xxxx
;                                   x       SPITBF, transmit buffer=20
full/empty
;                                    x      SPIRBF, receive buffer=20
full/empty
           mov     w0,SPI1STAT

           mov     #0b0000000100101101,w0  ;initialise at 368.64kHz
;                     xxx
;                        0                  Clk controlled by module
;                         0                 SDO controlled by module
;                          0                8-bit transfers
;                           0               input sampled in middle of bit
;                            1              CPHA =3D 0, data change on fall=
ing=20
edge
;                             0             /SS as normal I/O pin
;                              0            CPOL =3D 0, idle low
;                               1           Master
;                                011        secondary pre-scale  5:1
;                                   01      primary pre-scale   16:1 ->=20
368.64kHz (29.4912/80)
           mov     w0,SPI1CON1

           mov     #0xff,w0                ;supply CLK, wait for response
           call    send_w0                 ;with SDO high (FF data)
           bset    LATA,#ri                ;indicator
           btss    SPI1STAT,#SPIRBF        ;test for full receive buffer
           bra     $-2
           mov     SPI1BUF,w2              ;read buffer, *should* clear=20
SPIRBF
;           mov     SPI1BUF,w0              ;dummy reads ?
;           mov     SPI1BUF,w0
           mov     #0x30,w0                ;add #30 for display
           add     w0,w2,w0
           mov     w0,[w5++]               ;store in RAM for display later
           bclr    LATA,#ri                ;indicator

;           call    usec100                 ;delay ? no difference

           mov     #0xff,w0
           call    send_w0
           bset    LATA,#ri
           btss    SPI1STAT,#SPIRBF
           bra     $-2
           mov     SPI1BUF,w2
           mov     #0x30,w0
           add     w0,w2,w0
           mov     w0,[w5++]
           bclr    LATA,#ri

;           call    usec100

           mov     #0xff,w0
           call    send_w0
           bset    LATA,#ri
           btss    SPI1STAT,#SPIRBF
           bra     $-2
           mov     SPI1BUF,w2
           mov     #0x30,w0
           add     w0,w2,w0
           mov     w0,[w5++]
           bclr    LATA,#ri=20

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