If he keeps his packets smaller than the built in fifo (16 bytes) then he only has to empty it every 10mS - easily manageable with polling, depending on processor loading. If his packets are 16 to 20 bytes, then yes, it become more difficult, but it's not bad. He indicated that the packets will be less than 20 bytes, at 100Hz, so as long as interrupt latency is low there will be plently of time to handle it. -Adam On Mon, Aug 8, 2011 at 6:30 AM, Michael Rigby-Jones wrote: > >> -----Original Message----- >> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On > Behalf >> Of M. Adam Davis >> Sent: 06 August 2011 19:08 >> To: Microcontroller discussion list - Public. >> Subject: Re: [EE] the use of uart interupts on the ARM Cortex M0 >> >> The UARTs included in that series have 16 byte FIFO buffers built in. >> Further, the chip operates up to 50MHz. >> >> With the small, infrequent data load you are expecting, and the chip >> speed reasonably high, you can practically write it any way you like >> and the chip will be able to keep up - even if you follow your >> colleague's suggestion of putting more functionality into the ISR. >> >> If you can keep each packet of data at 16 bytes or less, you can even >> skip the ISR and just poll it - 100 Hz means you'd need to poll it >> more frequently than once every 10mS, and that's an eternity for a >> chip this fast. >> >> So, to put it bluntly, I suspect that you're spending too much time >> worrying about the details that aren't going to matter. =A0Code it up, >> test it out, and be done with it. Monitor the overrun and other error >> flags on the UART, and if you find a problem, try a different >> architecture for handling the stream. >> >> -Adam > > > The data rate required is 921.6Kbaud which is very high for a UART; the > 100Hz refers to the data packet rate. =A0As the OP mentions, this gives > only about 10us between bytes so it's most unlikely polling from the > main loop will be possible here, and I have to wonder if even an ISR > driven architecture will work reliably if there are other interrupts > running. > > IMO the requirements point toward the use of DMA. > > Regards > > Mike > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > This e-mail is intended for the person it is addressed to only. The > information contained in it may be confidential and/or protected by > law. If you are not the intended recipient of this message, you must > not make any use of this information, or copy or show it to any > person. Please contact us immediately to tell us that you have > received this e-mail, and return the original to us. Any use, > forwarding, printing or copying of this message is strictly prohibited. > No part of this message can be considered a request for goods or > services. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .