> -----Original Message-----
> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On
Behalf
> Of M. Adam Davis
> Sent: 06 August 2011 19:08
> To: Microcontroller discussion list - Public.
> Subject: Re: [EE] the use of uart interupts on the ARM Cortex M0
>=20
> The UARTs included in that series have 16 byte FIFO buffers built in.
> Further, the chip operates up to 50MHz.
>=20
> With the small, infrequent data load you are expecting, and the chip
> speed reasonably high, you can practically write it any way you like
> and the chip will be able to keep up - even if you follow your
> colleague's suggestion of putting more functionality into the ISR.
>=20
> If you can keep each packet of data at 16 bytes or less, you can even
> skip the ISR and just poll it - 100 Hz means you'd need to poll it
> more frequently than once every 10mS, and that's an eternity for a
> chip this fast.
>=20
> So, to put it bluntly, I suspect that you're spending too much time
> worrying about the details that aren't going to matter.  Code it up,
> test it out, and be done with it. Monitor the overrun and other error
> flags on the UART, and if you find a problem, try a different
> architecture for handling the stream.
>=20
> -Adam


The data rate required is 921.6Kbaud which is very high for a UART; the
100Hz refers to the data packet rate.  As the OP mentions, this gives
only about 10us between bytes so it's most unlikely polling from the
main loop will be possible here, and I have to wonder if even an ISR
driven architecture will work reliably if there are other interrupts
running.

IMO the requirements point toward the use of DMA.

Regards

Mike

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