On 29/07/2011 12:32, Forrest Christian wrote:
> On 7/29/2011 4:57 AM, Michael Rigby-Jones wrote:
>> What are you driving the 'Qinv' transistor base with - e.g. PIC I/O pin
>> or something with rather less drive capability?
> Yep, PIC I/O pin 3.3V...
>> What values are you using for R1, R2 and Rgate?
> 10K for both right now... may alter slightly to ensure the gate voltage
> doesn't go outside it's permitted range and/or add a 12V zener in
> parallel with R1.
>
> Rgate is zero right this second - wanted to eliminate that variable from
> the equation.   Will likely choose a very small value just big enough to
> ensure that the driver transistors do not have their current ratings
> exceeded as they switch.
>
> -forrest
>

I'm late looking at this, so sorry if I recycle anything (or just talk=20
rubbish :-) )
What part number are you using for Qinv? (and the others too out of=20
interest)
Also, what port (A, B etc) on the PIC is the pin part of, as some can=20
have better drive capabilities than others according to some of the=20
datasheets I have read, so this might be worth a check.
Have you tried bootstrapping (pos feedback with cap) the base?
Driving base with intermediate buffer with better specs?
The following info might help, what is the time you are seeing from: PIC=20
to Power MOSFET collector on, PIC to Qinv collector on (push-pull base),=20
PIC to Power FET base?
Is the overall latency from PIC pin turn on an issue, or just the Power=20
FET turn on? (or both?)
--=20
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