Sean Breheny wrote:

> Well, I agree that it is possible that the UART design reduces the
> probability of failure to a very small value even in the case where
> the first FF is often going metastable.

Not only that, the effects of any errors, when they occur, are well-underst=
ood
and controlled.

> I am curious - you mentioned that you have been designing plesiochronous
> systems for a long time. What is the application for these?

In the 1990s, I was designing terminal interfaces for T1 telephone circuits=
,
which are a 1.544 Mbit/sec digital service offered by the telephone company=
..
The usual mode of operation of these circuits is to have one end act as the
timing master, and the other end use "loopback timing" to generate its
transmit clock from its recovered receive clock. When the signal gets back =
to
the master, it is at the exact same frequency, but with a completely random
phase relationship (which is also perturbed by "jitter" and "wander").

Payload circuits, attached to the other side of our "terminal multiplexer"
(e.g., RS-422 data or AES3 digital audio) would use similar timing
arrangements, and this is where the bulk of my design work was. We actually
had off-the-shelf ICs (mostly Dallas Semiconductor) to handle most of the
details of the T1 circuit itself, but I still did some custom work on that
side, too.

> I actually knew the term "plesiosynchronous" (longer version of
> plesiochronous or different?) before but I thought it was distinct from
> "pseudosynchronous". My understanding was that plesiosynchronous referred
> to systems using the same clock frequency but different clock sources.
> Pseudosynchronous was one clock with clock and data skew.

According to http://en.wikipedia.org/wiki/Plesiochronous they are slightly
different terms, as you remember. What you are calling "pseudosynchronous" =
is
actually "plesiochronous." We never really made any distinction between the
two, and always used the shorter term.

-- Dave Tweed
--=20
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