Hi Dave,

Well, I agree that it is possible that the UART design reduces the
probability of failure to a very small value even in the case where
the first FF is often going metastable.

I am curious - you mentioned that you have been designing
plesiochronous systems for a long time. What is the application for
these?

I actually knew the term "plesiosynchronous" (longer version of
plesiochronous or different?) before but I thought it was distinct
from "pseudosynchronous" . My understanding was that plesiosynchronous
referred to systems using the same clock frequency but different clock
sources. Pseudosynchronous was one clock with clock and data skew.

Sean


On Sun, Jul 3, 2011 at 7:55 AM, Dave Tweed <pic@dtweed.com> wrote:
> [Sorry, the first version of this that got sent out may have been slightl=
y
> garbled.]
>
> Sean Breheny wrote:
>> The designers of the PICs thought of this, though, so they feed Out0 int=
o
>> yet another FF, generating Out1. Then, Out1 fans-out to several logic ga=
tes
>> which depend on the internal implementation details within the PIC.
>
> This is where your chain of suppositions breaks down. The designers of an=
y
> proper UART (or any other circuit dealing with asynchronous inputs) would=
 NOT
> fan out Out1 to multiple gates, except in carefully controlled ways in wh=
ich
> metastability is taken into consideration.
>
> The main thing Out0 and Out1 would be used for would be to feed a single =
gate
> that functions as an edge detector, and more likely than not, the output =
of
> that gate will be fed through a third FF (call it Out2).
>
> In the specific case of a UART, Out2 is used to synchronize a state machi=
ne
> that controls all of the rest of the logic of the UART receiver. This inc=
ludes
> the actual sampling of the data bits from the asynchronous input, making =
sure
> that the samples are taken near the middle of each bit window.
>
> The samples are probably taken from Out1, so that most effects of a noisy
> input are already filtered out, but as you point out, Out1 may occasional=
ly
> be in a metastable state (because of a noise spike, not because of the ac=
tual
> bit edge).
>
> So let's talk about metastability now. With regard to the edge detector
> (Out2), the only effect of metastability is to create a one-clock ambigui=
ty
> (jitter) in when it decides that the edge has occurred. The only effect o=
f
> this ambiguity is to to shift the sampling point(s) for the data by +/- 1=
/16
> of a bit near the center of the bit window. This is of no consequence
> whatsoever.
>
> With regard to the actual data bit sampling from Out1, the only effect of
> metastability is to create a bit error, and applications that use UARTs
> generally know how to deal with bit errors -- even those that occur in st=
art
> bits and stop bits. As a first line of defense, a lot of UARTs actually t=
ake
> three samples near the center of each bit cell and do a majority vote amo=
ng
> them.
>
> So, my overall point is, the designers of UARTs and other kinds of interf=
aces
> know about metastability and have many techniques for dealing with it. On=
ce
> these solutions are in place, plesiochronous operation causes no addition=
al
> problems.
>
> -- Dave Tweed
> --
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