Hi Veronica, Yes, I understand how UARTs work. Just as all logic circuits, they depend on internal consistency. If two signals within the UART are both supposed to be at the same value as the sampled input, but they instead differ because they come from two different logic gates which were "asked" to interpret an invalid logic level and they did so differently, then all bets are off. The 16x sampling is intended to help reduce noise sensitivity - it has nothing to do with the problem I am talking about. Sean On Sun, Jul 3, 2011 at 12:30 AM, Veronica Merryfield wrote: > > On 2011-07-02, at 8:57 PM, Sean Breheny wrote: > >> Let's make things more concrete: let's say I have two PICs >> communicating via their internal USARTs in asynchronous mode. > > In which case it doesn't matter a jot if the clocks are the same or not. = From a PIC data sheet on the UART... > > "The data recovery block operates at 16 times the baud rate, whereas the = main receive serial shifter operates at the baud rate. After sampling the U= xRX pin for the Stop bit, the received data in UxRSR is transferred to the = receive FIFO (if it is empty). > > The data on the UxRX pin is sampled three times by a majority detect circ= uit to determine if a high or a low level is present at the UxRX pin." > > Two things to note - > 1. the sampling of the data pin is at 16x the baud rate. This is common p= ractise for most UARTs and variants. > 2. the UART logic is looking for a level not an edge. > > However, there are other reasons why a common clock might not be a good i= dea but it can work out. > > > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .