Sean Breheny wrote:
> However, the following overview of metastability clearly shows it
> persisting for multiple clock events on a single FF (of course, this
> COULD be an error by the author):
>=20
> http://www.cs.gmu.edu/cne/pjd/PUBS/CACMcols/cacmNov07.pdf

I don't know what to say about that. Despite the excellent credentials of t=
he
author, it isn't a very rigorous article. What does a diode have to do with
this discussion? It has only one "input", not two. Too much hand-waving.

The metastability data comes from a paper published in 1973, and who knows
how much before that the data was actually taken, or what kind of flip-flop
technology was in use at that time? The use of narrow clock pulses suggests
that we're talking about non-master-slave latches.

> Moreover, a bigger reason why I am skeptical of your assertion is that it
> implies that it should be possible to make a totally metastable-free
> synchronizer as long as I make it have a delay of three clock cycles (i.e=
..,
> give the input FF two clock cycles to stabilize and then latch its output=
).

No, your logic is faulty. "... give the FF two clock cycles to stabilize ..=
.."
implies that you already have the means to reliably detect an input edge.
You can't have it both ways.

I never suggested that a metastable state could not propogate down a chain =
of
FFs, only that any one FF will be metastable for at most one clock cycle.

> While 3 or even 2 stage synchronizers can make the probability of
> metastability very small, every solid source I've seen says that it is
> impossible to eliminate it totally.

That is true.

Look at it this way: The metastable state can propogate from FF to FF,
because it occurs when the input and output are essentially at the same
voltage.

If that voltage is also close to the input threshold voltage of any logic
circuits (e.g., an AND gate functioning as an edge detector), then the outp=
ut
of that logic circuit can fluctuate randomly because of the effects of
internal noise added to the metastable voltage.

However, if the logic threshold of the gate is deliberately made different
from the metastable voltage (not hard to do, and a generalization of the
"threshold FF" idea), then the only result of the metastable state is to
introduce a one-clock ambiguity in when the output of the gate changes stat=
e.
And like I said before, most communications interfaces are designed to take
this kind of ambiguity in stride.

IC designers have given this a lot of thought in the almost 40 years since
that data was taken, and they have come up with solutions that are quite
effective. And they are NOT relying on "drift and jitter" as you put it in
your original post.

I have been designing "pseudosynchronous" (the actual term is "plesiochrono=
us")
interface circuits in FPGAs for 20 years, and I have never seen a failure o=
f
the type you are describing.

-- Dave Tweed
--=20
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