Sean Breheny wrote:
> The serious problems are things like internal signals within the destinat=
ion
> device (which are dependent on the input signal) staying in an indetermin=
ate
> state for several clock cycles.

No. Like I said, as long as the input signals stay in the same state for at
least two clocks at a time, no metastable state can last for more than one
clock cycle -- if the signal failed setup/hold on one clock edge, it will
meet it on the next.

In the end, the only ambiguity as far as the receiving logic is concerned
is whether the transition happened on CPU clock edge N or clock edge N+1.
Most protocols don't care about this kind of jitter, especially synchronous
protocols like SPI or I2C, which use a data clock which is a fraction of th=
e
CPU clock.

As far as the PCB layout goes, you already mentioned using a clock
distribution chip -- as long as each output goes to just one CPU, and the
lines are terminated properly, I don't see any problems there.

-- Dave Tweed
--=20
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