Hmmmm. First of all, there are various interfaces among the processors and some are SPI, which of course is synchronous (although to a clock signal which would normally be derived from a source which is asynchronous to the slave's clock) Secondly, I've been taught (and thought I understood properly) that asynchronous interfaces rely on asynchronicity. In other words, they actually require randomness over time in the relationship between the two clock domains. If there is a fixed relationship between the timebases of the source and destination devices, then there can be serious problems if this relationship causes them to be off by a narrow range of time. The serious problems are things like internal signals within the destination device (which are dependent on the input signal) staying in an indeterminate state for several clock cycles. This does not require that every single clock edge (of the destination timebase) have an accompanying transition on the signal line. There is some probability of an indeterminate state at every edge which violates the setup time. The more often the edges, the greater the overall probability of internal signals being indeterminate. This could be especially problematic for edge-triggered signals which are looking for changes in a signal on successive edges of the destination device's timebase clock. Sean On Thu, Jun 30, 2011 at 8:44 PM, Dave Tweed wrote: > Sean Breheny wrote: >> I'm having a disagreement with someone about how to handle a situation >> where there are several processors (two NXP ARM-type microcontrollers, >> a DSP, and two Freescale Power-PC microprocessors) on one PCB. To save >> money, he wants to use one oscillator for all of these and distribute >> it to them using clock distribution ICs. >> >> I think that this is unwise unless he takes great care to length-match >> the clock traces, control propagation velocity, etc. Otherwise, we >> could end up with metastability problems because we will likely have >> all of the processors operating in a pseudosynchronous mode and they >> intercommunicate with each other. > > Frankly, I wouldn't worry about it. You don't say what kind of communicat= ions > is being used among the different processors, but as long as the interfac= es > are designed to properly handle asynchronous signals (and most of them ar= e), > then pseudosynchronous signals cause no additional problems. > > If you think about it, the only way you get the "persistent metastable st= ate" > that you are hypothesizing is if the data lines change state on every sin= gle > CPU clock edge. As long as every data state lasts two or more clock CPU > periods at the pin, there will be no problem. > > -- Dave Tweed > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .