Nice question itself. Here is a thought. Could the clock line(s) pick up in=
terference since they would be *longer* than the standard practice?

John


--- On Fri, 7/1/11, Sean Breheny <shb7@cornell.edu> wrote:

> From: Sean Breheny <shb7@cornell.edu>
> Subject: [EE] Clock distribution on a PCB
> To: "Microcontroller discussion list - Public." <piclist@mit.edu>
> Date: Friday, July 1, 2011, 4:12 AM
> Hi all,
>=20
> I thought I could find something about this via a Google
> search but so
> far I have not found exactly what I need.
>=20
> I'm having a disagreement with someone about how to handle
> a situation
> where there are several processors (two NXP ARM-type
> microcontrollers,
> a DSP, and two Freescale Power-PC microprocessors) on one
> PCB. To save
> money, he wants to use one oscillator for all of these and
> distribute
> it to them using clock distribution ICs.
>=20
> I think that this is unwise unless he takes great care to
> length-match
> the clock traces, control propagation velocity, etc.
> Otherwise, we
> could end up with metastability problems because we will
> likely have
> all of the processors operating in a pseudosynchronous mode
> and they
> intercommunicate with each other. At boot time there will
> be a fixed
> timing relationship established between them, and it could
> well be
> that this ends up with two of them clocking together except
> for a tiny
> amount of variation due to different propagation delays. It
> could then
> be that every single bit communicated between them ends up
> right in
> the middle of the metastability window, with the result
> that the
> probability of bit errors is relatively high.
>=20
> I am advocating that each processor be run with separate
> clocks. Even
> if they are at the same frequency, the drift and jitter
> among them are
> almost certain to be greater than the difference in
> propagation delays
> so that instances where a transition violates setup and
> hold times for
> the input synchronizers will be only rare, random events
> rather than
> potentially every single transition.
>=20
> He agrees that in principle I am right but he thinks that
> this is
> really only a risk if you are trying to set up a
> synchronous digital
> system.
>=20
> My main question for all of you is this: where can I find
> some web
> reference material which talks about clock hazards in
> nominally
> asynchronous digital systems? Everything I can find seems
> to assume
> that you are trying to set up all of the chips in
> lock-step
> synchronous operation.
>=20
> Secondarily, any opinions on this would be appreciated.
>=20
> Thanks,
>=20
> Sean
> --=20
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>=20
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