On 22/06/2011 02:02, Barry Gershenfeld wrote:
> It may or may not turn out to be that important, but I wanted to explore =
the
> options when it comes to generating low-rate PWM.  I'm always surprised a=
t
> how limited the dividers are with this.  If there's anything that would b=
e
> easy to do inside the chip, it would be to divide some slow clocks down t=
o
> even slower clocks.  So, here are the options I came up with.

Do it in SW with a software counter driven by timer interrupt. You only=20
need PWM HW for higher speeds. You then can be as slow as you like.

I tend to have one timer ISR for whatever needs most frequent attention=20
and then a bunch of software counters for less frequent tasks. These can=20
set a flag read by main "do forever" loop if the response time isn't=20
critical. The main loop must reset the flag.
--=20
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