Hi,

I'm hoping that someone more experienced with stepper motors than I can she=
d
some light on a problem I'm having.  I am using a PIC18F2410 with a MAX5820
DAC and a pair of LMD18245 H-bridges to drive a hybrid stepper motor within
a speed range of 2.4 RPM to 192 RPM.  The motor produces a great deal of
audible noise between ~70 RPM and 100 RPM, which I'm attempting to reduce.
 The I2C interface to the MAX5820 isn't fast enough to maintain a 1/32nd
microstep increment through the entire speed range of the motor, so I
increase the microstep increment at the following threshholds: 1/16th
microstepping above 45 RPM, 1/8th microstepping above 84 RPM, and then 1/4
microstepping above 120 RPM.

Background on the circuit:

This is a sine-cosine microstepping chopper drive.  The MAX5820 has each of
its outputs connected to the Vref pin on one of the LMD18245s, to provide
the chopping currrent level.  The PIC sets the maximum current level at 1.4=
A
using the LMD18245's internal DAC's at startup, and leaves them the same
after that.  I've verified with a scope and logic analyzer that the I2C
communications between the PIC and the MAX5820 are working, and the MAX5820
is outputting 2 stepped sine waves.  I've also checked with National's tech
support, and they've told me the circuit looks good.

Here's the weird part:

When I view the CSOUT pin on one of the LMD18245s, it follows the curve of
the Vref pin for most of the step period, but as the motor speed increases,
there is a flattened region of the CSOUT waveform right before the zero
crossing, shown in these scope images with CSOUT on the top and Vref from
the MAX5820 on the bottom (zoomed out timescale:
http://s1218.photobucket.com/albums/dd411/picster733/?action=3Dview&current=
=3Dzoomedout.jpg)
(zoomed-in timescale:
http://s1218.photobucket.com/albums/dd411/picster733/?action=3Dview&current=
=3Dzoomedin.jpg
)

As the motor speed increases further, the flattened region changes to a
second peak in the current.  Concerned that the LMD18245's internal
comparator wasn't switching at the right times, I viewed the COMPOUT pin on
the scope (bottom) along with the CSOUT pin (top), and during the time that
the current is rising to the second peak, COMPOUT is low, indicating that
the low-side switch of the H-bridge should be off, forcing the current to
recirculate through the high-side switch and the opposing high-side
intrinsic diode.  Image here:
http://s1218.photobucket.com/albums/dd411/picster733/?action=3Dview&current=
=3D0615111856.jpg.
 This second peak is most apparent at the motor speeds that produce the
worst audible noise, so I believe that the non-sinusoidal current waveform,
with it's sharp drop to zero when the DIR input switches, is the cause of
the noise.  The state of the COMPOUT pin makes sense, because the motor
current detected on the CSOUT pin is higher than the current level set by
Vref and the internal DAC.

So my question is, how can the current be increasing during this time, and
what can I do to fix this problem?

Note: the maximum current level was set at 1.88A for the photos I took, but
reducing the maximum current with the internal DAC's merely reduced the
amplitude of the CSOUT waveform proportionally, without any apparent change
in shape.

Thanks,
Jim
--=20
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