On 08/05/2011 16:09, V G wrote: > On Sun, May 8, 2011 at 10:46 AM, Oli Glaser wro= te: >> At the very least - I made a 2-layer test board for a 64 pin FPGA that >> "worked", but for any serious use you need power and ground planes for >> decoupling and controlled impedance purposes, plus the extra routing >> space. Look into high speed digital techniques and you will see why all >> this is necessary. Xilinx should have some relevant documentation on >> their site, about the optimum setup for their chips, how many IOs can >> switch at once, thermal considerations, etc. > Looks like I need a degree in EE. > > I'll go sit in the EE lectures at my university in my spare time next > year. This looks like some serious stuff. Didn't mean to put you off, it's not too difficult if you do some=20 reading before hand. If you are not intending to push them to the limits=20 then you can get away with a lot more, and a 2 layer board might be=20 okay. Most of my work with FPGAs has been at high speeds (core and I/O)=20 so I have seen the effects of an unsuitable board. Best way to find out and learn is just to jump in a try it, it won't=20 seem so bad when you get going. I would maybe select a TQFP package to=20 make life easier on yourself, but a BGA is certainly possible with=20 various techniques documented all over the web. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .