On 05/05/2011 12:47, Herbert Graf wrote:
> On Thu, 2011-05-05 at 02:40 -0400, V G wrote:
>> On Thu, May 5, 2011 at 1:26 AM, Xiaofan Chen<xiaofanc@gmail.com>  wrote:
>>> I am a beginner as well (and my object is more modest than you --
>>> just to learn some ABCs, not going to do coding). I think the following
>>> URL has a good explanation.
>>> http://www.asic-world.com/tidbits/wire_reg.html
>> I've been linked to that site many times through various sources, and
>> read it, but for some reason it still doesn't help me.
>>
>> I guess I'm the kind of guy who needs to know *exactly* what's going
>> on at the gate level to really understand it. I'll see how it works in
>> a simulator or Synplify or something.
> You are writing in HDL. HDL is stands for "hardware description
> language". You AREN'T WRITING GATES, you're writing a description of
> hardware that a tool (the synthesizer) will analyze and infer logic to
> do what you're asking.
>
> Whether you use a wire or reg depends on what construct you use (simply:
> wires are connect to the outputs of instantiated modules, or assigned to
> by an assign statement, regs are written to by an always block).
>
> Here's something to consider, have a look at these assign statements and
> assume your compiling for an FPGA:
>
> input in1, in2;
> output out;
> wire net1;
> assign net1 =3D !in1;
> assign out =3D net1&  in2;
>
> You might assume that the synthesizer will do the following:
>
> in1 ->  (not) ->  net1 ->  (
> 		        (and) ->  out
> in2 ------------------>  (
>
> And you might assume that net1 is a wire in your FPGA.
>
> You'd be wrong.
>
> If you open up FPGA Editor/Planahead you'd discover that Net1 doesn't
> exist in your FPGA. The reason is the synthesizer will combine the two
> assign statements into one LUT element. Even though you declared net1 as
> a wire, it won't exist as a wire in the FPGA.
>
> Remember, you are guiding the tool with your HDL, you're not telling the
> tool which gates to use.
>
> TTYL
>

Good clear post

Vote ++

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