On Thu, May 5, 2011 at 7:59 AM, Herbert Graf <hkgraf@gmail.com> wrote:
> You're main isn't calling your submodule, so it's being eliminated.
>
> Like in C there is only one "main". In Verilog the "root" module is the
> top of the tree.
>
> In your case, change main as follows:
>
> module main(
> =A0 =A0 =A0 =A0input wire clk,
> =A0 =A0 =A0 =A0output reg [7:0] Led,
> =A0 =A0 =A0 =A0output [3:0] an,
> =A0 =A0 =A0 =A0output [6:0] seg
> =A0 =A0 =A0 =A0);
>
> =A0 =A0 =A0 =A0reg [32:0] count;
>
> =A0 =A0 =A0 =A0always @ (posedge clk) begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0count =3D count + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Led[7:0] =3D count[27:20];
> =A0 =A0 =A0 =A0end
>
> =A0 =A0 =A0 =A0led_mux unit0(.clk(clk), .an(an), .seg(seg) );
>
> endmodule
>
> Remember, just because something is labeled "output" or "input" it
> doesn't mean it's actually leaving the chip. Those declarations only
> have relevance to that module. In your case, clk is an input to led_mux,
> and an and seg are outputs to led_mux.
>
> A "module" is a chunk of logic, similar to how a function in C is a
> chunk of code.


Thanks. That works, but lets say the main module gets complicated and
has a million inputs and outputs (in the parenthesis). I wanted to
declare all those only in the led_mux  module and not in the main
module up top. How can I do that? Why is it necessary to add the an
and seg outputs to the main module? Why can't the led_mux module
handle those on its own?

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