On Thu, 2011-05-05 at 07:26 -0400, V G wrote:
> Next question: I wrote a simple program to display the value of a
> register on 8 LEDs. At the same time, a 4-digit 7-segment display is
> multiplexed to show some numbers.
>=20
> Single module version: http://pastebin.com/mYv7HVfy This one works.
> Everything works as expected.
>=20
> Two module version: http://pastebin.com/BbXkrWBW This one doesn't work
> and I don't know how to make it work. I tried to split the
> functionality into two modules and now the functionality of the
> 7-segment multiplexer is lost. What went wrong here?
>=20
> Also, what exactly are modules in Verilog?

You're main isn't calling your submodule, so it's being eliminated.

Like in C there is only one "main". In Verilog the "root" module is the
top of the tree.=20

In your case, change main as follows:

module main(   =20
        input wire clk,
        output reg [7:0] Led,
        output [3:0] an,
        output [6:0] seg
        );
       =20
        reg [32:0] count;
               =20
        always @ (posedge clk) begin
                count =3D count + 1;
                Led[7:0] =3D count[27:20];               =20
        end
       =20
        led_mux unit0(.clk(clk), .an(an), .seg(seg) );
       =20
endmodule

Remember, just because something is labeled "output" or "input" it
doesn't mean it's actually leaving the chip. Those declarations only
have relevance to that module. In your case, clk is an input to led_mux,
and an and seg are outputs to led_mux.

A "module" is a chunk of logic, similar to how a function in C is a
chunk of code.

TTYL


--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.