On Thu, 2011-05-05 at 15:33 +0800, Xiaofan Chen wrote: > On Thu, May 5, 2011 at 2:40 PM, V G wrote: > > On Thu, May 5, 2011 at 1:26 AM, Xiaofan Chen wrote= : > >> I am a beginner as well (and my object is more modest than you -- > >> just to learn some ABCs, not going to do coding). I think the followin= g > >> URL has a good explanation. > >> http://www.asic-world.com/tidbits/wire_reg.html > > > > I've been linked to that site many times through various sources, and > > read it, but for some reason it still doesn't help me. >=20 > I think one thing is that you need to use reg for sequential logic. >=20 > "Something that we need to know about reg is that it can be used for > modeling both combinational and sequential logic. Reg data type can > be driven from initial and always block." initial blocks are not synthesizer and should NOT be used for FPGA designs, except for test bench blocks only used during simulation. If you need something initialized, use reset, that's what it's for. TTYL --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .