On Thu, 2011-05-05 at 00:59 -0400, V G wrote:
> Here is my (short and simple) Verilog code to make an array of LEDs blink=
..
> It works.
>=20
> http://pastebin.com/guQcNkwp
>=20
> But note that in the module, the LED array is declared as an output reg.
> Initially, I tried to use an output wire because I thought a "wire" was
> necessary to route a signal to a pin or something. But then I got an erro=
r
> so I changed it to reg and it works, but I don't know why. I don't really
> understand how the register is being routed to the pins of the LEDs.
>=20
> I don't *really* understand the difference between a wire and reg, and no=
ne
> of the books I've been reading explain that. Can anyone help?

A reg is assigned by an always block.
A wire is assigned by either the output of the sub-block, or an assign
statement.
That's all there is to know.

It's a syntax thing.

--=20
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