On Thu, May 5, 2011 at 5:01 AM, Michael Watterson <mike@radioway.org> wrote=
:
> That's not important.
>
> What's important is how to to take a problem/application and define the
> logic, know which parts are sequential or synchronous etc...

I agree, that too is part of the problem.

> The whole point of Verilog and VHDL is to actually hide the
> implementation details. Tools exist to convert the FPGA design to an ASIC=
..

You could say the same for C. The whole point is to hide the low level
stuff generated by the compiler. All I'm saying is, personally, I need
to know what's being hidden so I can truly understand what's going on.

> When you have entered a design you can without leaving the Xilinx IDE
> simply click and see the equivalent schematic as if the design was
> implemented in gates, counters and registers. You can actually also see
> how it's been mapped to the physical RAM based LUT, and physical
> registers, Latches, gates and multipliers the FPGA has.
>
> The main difference between "modern" FPGA and original programable
> logic, is the original parts (Still somewhat in CLPD) in 1980s used
> array of NANDs and NOR with matrix of wires and "fusable" links.
>
> In college we took same design and 1st did it with whatever logic gates
> needed. Then we also simply took a truth table of the design and
> programmed it into an EPROM with inputs on address lines and output as
> output. If there where states, then D-Type latches connected some output
> pins to some input addresses.
>
> The FPGA replaces the fusable links with RAM and and the EPROM with RAM.
> Hence unless the FPGA has onboard Flash, the entire configuration is
> lost at power off and at power on it must be loaded from a cpu or
> external Flash Memory.
>
> A processor fetches one or two instructions at a time under program
> control from Flash. An FPGA loads ALL of the Flash to define the LUT
> (look up tables) and interconnection wiring multiplexing/definitions
> (also a form of RAM). Since RAM is very fast and LUT latency is just the
> RAM access time, FPGA is very fast. An individual logic gate may be
> fast, but the more complex the logic, the more gates are used and
> latency increases and also risk of race conditions. The LUT, if big
> enough has same latency no-matter the logic table and no internal "race"
> conditions.
>
> Unless you are near the capacity of the FPGA, or near the speed
> constraints, you don't need to know how it works. That's the whole point
> of Verilog and VHDL. You do need to know how you would design a solution
> to system with Logic.

I guess you don't *need* to know, but I certainly *want* to know.
--=20
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