On 05/05/2011 08:53, V G wrote:
> Conceptually, I know how transistors are used to make logic gates, and
> how those gates can be packaged into an IC.

That's not important.

What's important is how to to take a problem/application and define the=20
logic, know which parts are sequential or synchronous etc...

The whole point of Verilog and VHDL is to actually hide the=20
implementation details. Tools exist to convert the FPGA design to an ASIC.

When you have entered a design you can without leaving the Xilinx IDE=20
simply click and see the equivalent schematic as if the design was=20
implemented in gates, counters and registers. You can actually also see=20
how it's been mapped to the physical RAM based LUT, and physical=20
registers, Latches, gates and multipliers the FPGA has.

The main difference between "modern" FPGA and original programable=20
logic, is the original parts (Still somewhat in CLPD) in 1980s used=20
array of NANDs and NOR with matrix of wires and "fusable" links.

In college we took same design and 1st did it with whatever logic gates=20
needed. Then we also simply took a truth table of the design and=20
programmed it into an EPROM with inputs on address lines and output as=20
output. If there where states, then D-Type latches connected some output=20
pins to some input addresses.

The FPGA replaces the fusable links with RAM and and the EPROM with RAM.=20
Hence unless the FPGA has onboard Flash, the entire configuration is=20
lost at power off and at power on it must be loaded from a cpu or=20
external Flash Memory.

A processor fetches one or two instructions at a time under program=20
control from Flash. An FPGA loads ALL of the Flash to define the LUT=20
(look up tables) and interconnection wiring multiplexing/definitions=20
(also a form of RAM). Since RAM is very fast and LUT latency is just the=20
RAM access time, FPGA is very fast. An individual logic gate may be=20
fast, but the more complex the logic, the more gates are used and=20
latency increases and also risk of race conditions. The LUT, if big=20
enough has same latency no-matter the logic table and no internal "race"=20
conditions.

Unless you are near the capacity of the FPGA, or near the speed=20
constraints, you don't need to know how it works. That's the whole point=20
of Verilog and VHDL. You do need to know how you would design a solution=20
to system with Logic.

--=20
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