On Thu, May 5, 2011 at 1:25 AM, Lorenzo Luengo C. wr= ote: > I think the explanation is very intuitive. When you do an assignment > (i.e "Led[7:0] <=3D 8'b11111111;", line 14), you need something to hold > the value, somthing an ideal wire cannot, so you need a register (an > array of D flip-flops). > > If you declared Led as a wire, you could do this like a logic > description statement, like "Led [7:0] =3D count[22];". In this case the > register "count" holds the value, and you're tapping this value onto all > eight wires in the Led array (my syntax maybe not all correct, you may > need to use replication braces {}), and put this outside the "always @" > block, because you are describing a connection, not an event or behavior. Thanks. That makes more sense. > It's been nice to see this thread... it made me remember my student > times when doing some assignments in FPGAs :D Oh no, it's not actually an "assignment", I just do this stuff for fun. I meant the Verilog keyword assignment type of thing. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .