El 05/05/2011 0:59, V G escribi=F3:
> Here is my (short and simple) Verilog code to make an array of LEDs blink=
..
> It works.
>
> http://pastebin.com/guQcNkwp
>
> But note that in the module, the LED array is declared as an output reg.
> Initially, I tried to use an output wire because I thought a "wire" was
> necessary to route a signal to a pin or something. But then I got an erro=
r
> so I changed it to reg and it works, but I don't know why. I don't really
> understand how the register is being routed to the pins of the LEDs.
>
> I don't *really* understand the difference between a wire and reg, and no=
ne
> of the books I've been reading explain that. Can anyone help?

I think the explanation is very intuitive. When you do an assignment=20
(i.e "Led[7:0] <=3D 8'b11111111;", line 14), you need something to hold=20
the value, somthing an ideal wire cannot, so you need a register (an=20
array of D flip-flops).

If you declared Led as a wire, you could do this like a logic=20
description statement, like "Led [7:0] =3D count[22];". In this case the=20
register "count" holds the value, and you're tapping this value onto all=20
eight wires in the Led array (my syntax maybe not all correct, you may=20
need to use replication braces {}), and put this outside the "always @"=20
block, because you are describing a connection, not an event or behavior.

It's been nice to see this thread... it made me remember my student=20
times when doing some assignments in FPGAs :D


--=20
Lorenzo Luengo Contreras
Ingeniero Civil Electr=F3nico
Laboratorio MIDGEO (LF-106)
Facultad de Ciencias F=EDsicas y Matem=E1ticas
Universidad de Concepci=F3n
Concepci=F3n - Chile
+56-41-2207400
http://midgeo.udec.cl

--=20
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