On Tue, 2011-05-03 at 19:16 -0400, V G wrote:
> Hey all,
>=20
> I'm now reading into the inner workings of FPGAs to better understand how
> they work. The look up table seems to be the most confusing part for me.
>=20
> 1. I don't really understand what it IS or what it DOES. Can anyone pleas=
e
> explain? I know a logic cell in a Spartan 3e FPGA, for example, contains =
a 3
> input LUT and a DFF, but I don't understand what the LUT does or what it'=
s
> made of (gate wise).

Physically a LUT is actually composed of two things: a MUX and an SRAM.

The select pins of the MUX are the inputs to the LUT, the inputs to the
MUX are connected to the dedicated SRAM.

a 3 input LUT contains a MUX with 3 select lines and 8 input lines
connected to an 8 bit SRAM.

> 2. Does the LUT itself provide the logic functionality? As in AND, OR, XO=
R,
> NOT, whatever gates? If so, where are the inputs to the gates, and what a=
re
> the LUT inputs for?
>
> 3. What kind of "function" can LUTs provide?

A 3 input LUT can perform ANY combinational function that has 3 inputs
and 1 output. That's what makes LUTS so powerful. A 3 input LUT can
easily replace several "standard" logic cells. One of the roles of the
synthesizer is to combine combinational logic in a way as to cram as
much functionality into each and every LUT.

When you "program" an FPGA, one of the things you are doing is loading
the contents of every SRAM connected to a LUT.

TTYL

--=20
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