On Sun, 2011-05-01 at 17:10 +0100, Oli Glaser wrote: > On 01/05/2011 16:35, Herbert Graf wrote: > > On Sun, 2011-05-01 at 07:05 +0100, Oli Glaser wrote: > >> On 01/05/2011 06:54, V G wrote: > >>> On Sun, May 1, 2011 at 12:31 AM, Oli Glaser = wrote: > >>> > >>>> When you compile your design, have a look at the "schematic" in Mode= lSim > >>>> (or whatever Xilinx uses) > >>>> This is a graphical representation of your design. > >>>> > >>> Thanks. I didn't know this was possible. This should help a lot. > >> Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not > >> ModelSim. > > Synplify is actually a many thousands of dollars tool. Floorplanner is > > the tool in ISE that lets you see a schematic view of your routed > > design. > > > > TTYL >=20 > In the free version Actel IDE they use Synplify, and ModelSim for=20 > simulation, both launch from the main software (Libero) > I thought Xilinx might do something similar. Wow, really? I didn't know that. Synplify is a very powerful tool, I'm surprised they include it in any free version of anything! I wonder if Actel simply decided to use Synplify for all synthesis instead of developing it's own synthesizer? AFAIK the webpack for Xilinx only has XST (the Xilinx synthesizer) available, and for view what's in the FPGA you use either FPGA editor (the older tool) or Planahead (the new tool that I haven't been able to play with much yet). TTYL --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .