On 01/05/2011 16:35, Herbert Graf wrote:
> On Sun, 2011-05-01 at 07:05 +0100, Oli Glaser wrote:
>> On 01/05/2011 06:54, V G wrote:
>>> On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<oli.glaser@talktalk.net>   =
wrote:
>>>
>>>> When you compile your design, have a look at the "schematic" in ModelS=
im
>>>> (or whatever Xilinx uses)
>>>> This is a graphical representation of your design.
>>>>
>>> Thanks. I didn't know this was possible. This should help a lot.
>> Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not
>> ModelSim.
> Synplify is actually a many thousands of dollars tool. Floorplanner is
> the tool in ISE that lets you see a schematic view of your routed
> design.
>
> TTYL

In the free version Actel IDE they use Synplify, and ModelSim for=20
simulation, both launch from the main software (Libero)
  I thought Xilinx might do something similar.


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