On Sat, 2011-04-30 at 23:06 -0700, William "Chops" Westfield wrote:
> On Apr 30, 2011, at 5:19 AM, Herbert Graf wrote:
>=20
> > Wires CANNOT be "written" to by an always block. They can only be =20
> > driven
> > by the instantiation of another block, or assigned to by an assign
> > statement.
> >
> > In your case, you're driving ssreg in an always block. As such, you =20
> > have
> > to declare ssreg as a "reg".
>=20
> Interesting.  This decoder is entirely combinatorial; how would it be =20
> written to use plain wires as outputs ?   (without knowing anything at =20
> all about verilog, and only a little about PLDs, that's sort of what I =20
> would have expected "always" block to do...)

As I explained in another post, "reg" in verilog does NOT necessarily
mean storage in the synthesized hardware. A properly written case
statement can result in just combinational logic (note that if you don't
properly write it you can infer latches very easily).

If one is "allergic" to the reg statement, a case statement can be
written something like this:

assign ssreg =3D (control =3D=3D FIRST) ? first_data :
		(control =3D=3D SECOND) ? second_data :
		(control =3D=3D THIRD) ? third_data : fourth_data;

Or something like that, it's personal preference which one prefers.
There is more room for error in this form, but it's much more flexible
then the case type structure.

TTYL

--=20
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