On Sun, 2011-05-01 at 07:05 +0100, Oli Glaser wrote:
> On 01/05/2011 06:54, V G wrote:
> > On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<oli.glaser@talktalk.net>  w=
rote:
> >
> >> When you compile your design, have a look at the "schematic" in ModelS=
im
> >> (or whatever Xilinx uses)
> >> This is a graphical representation of your design.
> >>
> > Thanks. I didn't know this was possible. This should help a lot.
>=20
> Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not=20
> ModelSim.

Synplify is actually a many thousands of dollars tool. Floorplanner is
the tool in ISE that lets you see a schematic view of your routed
design.

TTYL


--=20
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