On Sun, 2011-05-01 at 05:31 +0100, Oli Glaser wrote:
> On 30/04/2011 19:34, V G wrote:
> >   But I don't understand what a "reg" does and
> > what it really does inside the chip.
>=20
> A reg is short for register, e.g. a place to store bits, usually one or=20
> more D type flip-flops.

Actually that is not really true. reg does indeed stand for register,
but it doesn't necessarily mean storage in synthesized hardware. What it
actually means is the simulator running that code needs storage to
implement the logic writing that net.

For example, level sensitive always blocks (vs. edge sensitive) can
often result in logic the doesn't contain any storage in the final
synthesized hardware. Case in point: the following code requires a reg
declaration, but results in zero storage:

reg out;
always @ (in and reset)
begin
	if (reset)
	begin
		out <=3D 0;
	end
	else
	begin=09
		out <=3D in;
	end
end

Of course, this block COULD have be written as such, and therefore not
requiring a reg definition for out:

assign out =3D (reset) ? 1'b0 : in;

Which is much closer to the actual logic that would be produced, which
would probably be something like this:

reset -> (NOT) -> (   )
                  (AND) -> out=09
in -------------> (   )

Remember, that although it's called a reg in verilog, it doesn't
actually mean a flop.

Another place to be VERY careful with FPGAs is inferred latches. I'll
just say that whatever you do, make sure your code doesn't produce
latches (unless that's exactly the structure you need), you'll avoid
numerous issue down the road. Stick with D flip flops if you can.

TTYL
=09

--=20
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