On Apr 30, 2011, at 5:19 AM, Herbert Graf wrote:

> Wires CANNOT be "written" to by an always block. They can only be =20
> driven
> by the instantiation of another block, or assigned to by an assign
> statement.
>
> In your case, you're driving ssreg in an always block. As such, you =20
> have
> to declare ssreg as a "reg".

Interesting.  This decoder is entirely combinatorial; how would it be =20
written to use plain wires as outputs ?   (without knowing anything at =20
all about verilog, and only a little about PLDs, that's sort of what I =20
would have expected "always" block to do...)

BillW

--=20
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