On 01/05/2011 06:54, V G wrote:
> On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<oli.glaser@talktalk.net>  wro=
te:
>
>> When you compile your design, have a look at the "schematic" in ModelSim
>> (or whatever Xilinx uses)
>> This is a graphical representation of your design.
>>
> Thanks. I didn't know this was possible. This should help a lot.

Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not=20
ModelSim.

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