On Sat, Apr 30, 2011 at 4:05 AM, Oli Glaser <oli.glaser@talktalk.net> wrote=
:

> Roughly, a module is simply a reusable chunk of your design (a bit like
> a class in C++)
> So you define your e.g. counter, then instantiate it where you want to -
> like with your code, in your second module, you declare an instance of
> the first one.
> A parameter is for putting a meaningful name to some variable which can
> be changed easily (bit like a define in C - you don't have change all
> the places it's used, just the definition value)
> The parameter can be set when instantiating a module. For example you
> could have:
>
> module hex_to_sseg
> #(parameter WIDTH =3D 8)
>     (
>     input wire [3:0] hex,
>     output reg [WIDTH - 1:0] sseg
>     );
>
> ...rest of module.... (you would have to change all the "7s" in your
> module to "WIDTH - 1")
>
> Then when instantiating you could alter the default to create a 16 bit
> width:
> hex_to_sseg sseg_ #(.WIDTH (16)) unit_0(.hex(sw[3:0]), .sseg(seg));
>
> Note - take the C analogies very lightly, the best I could come up with
> to give a rough idea.
> This should all be explained in most starter tutorials or the first
> chapter of Verilog books.
>
> > Maybe I should do VHDL first...
>
> It will be just as steep a learning curve :-)
>
>

Whoops, I should have said "the things in the module brackets". I didn't
actually mean the parameter keyword. I don't really understand the things i=
n
the brackets and why they go in the brackets. I'm trying to picture a modul=
e
as an integrated circuit chip and the things in the brackets as pin
definitions as input/output. But I don't understand what a "reg" does and
what it really does inside the chip.
--=20
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