On Thu, 2011-04-21 at 03:00 -0400, V G wrote:
> I somehow managed to write a Verilog program and get it running on the
> board, no thanks to the poorly written tutorials. Everything seems to be
> working fine, except for a dimly lit segment on each of the displays, whi=
ch
> I also noticed with the test design. I emailed them about it. Hopefully,
> I'll get a free board.

You won't. By default some FPGAs enable week pull ups on their IOs, it's
an option during configuration, I'd bet that's what you're seeing.

TTYL

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